High level Synthesis Tools for FPGAs: A new revolution

María Freire Hermelo | Researcher

 

The evolution of programmable devices, like FPGAs, has greatly accelerated in the last years, in an attempt to satisfy market demands. Some of the most important ones are the reduction of time necessary to develop a product with regard to ASICs or the greater exploitation of parallelism by FPGAs in comparison with CPUs or even GPUs. Although these demands are extremely ambitious, the solutions that major manufacturers, as Altera, with OpenCL SDK, and Xilinx, with Vivado HLS, are setting in motion are no less ambitious.

One of the first advances, which meant a revolution in architectures, was the launch of SoC (System on Chip) devices that integrate in one chip processor and programmable logic; that is, software and hardware. This duality allows SoC to gather the best of both worlds: the flexibility and reduced development time of software and the high throughput of hardware. However, the difficulty in the design of systems for SoC devices is achieving the trade-off that provides the end product with the desired programmability without giving up speed. An efficient solution would be to implement in the programmable logic the software functions that consume more execution time. This alternative is leading to a new revolution led by high-level synthesis tools that translate the functions meant to be accelerated in synthesizable code in the FPGA.

These synthesis tools, as Vivado HLS and OpenCL SDK, allow generating a FPGA implementation from a processor implementation in a high-level language. It saves having to make an additional hardware design where the developer would implement again the algorithm in a hardware description language (VHDL or Verilog), managing the FPGA logic: resources, transfers between registers…

For instance, in the case of Vivado HLS, the algorithm is designed in C/C++/System C and it is debugged within the same development environment. Afterwards, the algorithm is synthesized by generating the hardware code or RTL, being necessary to add the suitable directives to get a good performance in terms of latency and throughput. Finally, the RTL generated is exported to a block with the interface that is more adequate to the system in which it will be integrated.

In the case of the Altera OpenCL SDK, implementation is done in OpenCL, a standard of parallel programming of heterogeneous systems. From then on, the design flow is very similar to the Vivado HLS one. The Altera SDK converts automatically kernel functions into hardware accelerators, adding the appropriate interfaces.

So, in an initial analysis, these tools seem to satisfy the market demands laid out at the beginning of this article. On one hand, they automate some of the most complex process in the hardware design flow, reducing the development time of a product compared with ASICs. On the other hand they allow to implement in logic the software functions that consume more CPU cycles, speeding their execution.

Being aware of the potential of these tools, Gradiant is keeping a close monitoring of their evolution and developing capacities in this field.

 

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